This application claims priority to U.S. Provisional Application No. 61/016,798 filed Dec. 26, 2007. The present invention relates generally to a semiconductor memory device, and more particularly to a memory device with improved word line structure having reduced RC delay time, lower power consumption, and higher device performance.
Word lines of conventional semiconductor memory devices are usually made of polysilicon material, and thus they have relatively high resistivity. One conventional technique to reduce IR drops and RC time delay along the word lines is to electrically couple each of the polysilicon word lines to a corresponding overlying metal strips (usually metal 2 layer). Such conventional technique poses new problems as device feature size further decreases in the sub-65 nm geometry.
One of the new problems includes an abrupt increase of the lateral parasitic capacitance as the metal width becomes less than 1.5 □m, resulting in an increased RC time delay and significant IR drop along the word line and various device performance degradations in the sub-65 nm technology. As illustrated in FIG. 2, RC delay time (Y-axis) increases abruptly as metal width (X-axis) becomes less than 1.5 □m.
Therefore, the present invention recognizes these drawbacks in conventional memory devices and provides an improved word line structure that prevents degradation of RC time delay and other device performance in the sub-65 nm technology nodes.